This invention relates to a thin-film transistor, a method for manufacturing the same, and a liquid crystal display device using the transistor.
Liquid crystal display devices have wide utility as display devices capable of realizing lightweight, miniaturization, and thinning. Among them, twisted nematic mode (TN mode) active matrix liquid crystal devices are widely known as a display device whose drive voltage is low with an attendant low power consumption and which is high in contrast and is able to provide high-quality images.
FIG. 7 shows a typical prior art thin-film transistor having a top gate structure provided in this type of liquid crystal device. A thin-film transistor A of the prior art is arranged such that it includes an island-shaped semiconductor unit 2 on a transparent substrate 1, an insulating layer 3 formed on the substrate 1 to cover the semiconductor unit 2 therewith, a source electrode 4 and a drain electrode 5 connected via the insulating layer 3 to the semiconductor unit 2, an insulating layer 6 to cover them as shown, and a pixel electrode 7 formed on the insulating layer 6.
The semiconductor unit 2 is constituted of a channel formation portion 8 at the center thereof, and a source region 9 and a drain region 10 formed to sandwich the channel formation portion 8 therebetween from opposite sides thereof. The source electrode 4 is connected to the source region 9 and the drain electrode 5 is connected to the drain region 10, and the pixel electrode 5 is connected to the drain electrode 5. A gate electrode 12 is formed within the insulating layer 3 above the channel formation portion 8 via a gate insulating layer 11.
In the structure depicted in FIG. 7, the semiconductor unit 2 is generally constituted of an amorphous silicon or a polysilicon, the source electrode 4 and the drain electrode 5 are constituted of conductive metal materials, and the pixel electrode 7 is constituted of a transparent conductive film such as ITO (indium tin oxide). The thin film transistor A of this example has a structure such that a load in the channel formation portion 8 is controlled by the action of electric field generated by the gate electrode 12 to thereby obtain the operation as a switch.
In the structure depicted in FIG. 7 wherein the pixel electrode 7 is indirectly connected to the drain region 10 via the drain electrode 5, an insulating layer 6 is freshly formed after the formation of the drain electrode 5. This essentially requires the formation of a contact hole in the insulating layer 6, after which the pixel electrode 7 has to be formed, thus presenting the problem that the manufacturing process becomes complicated. Especially, there arises the problem that for the formation of the contact hole in the insulating layer 6, an additional mask is required in a photolithographic step.
It may occur to one that using the structure shown in FIG. 8, a connection terminal 7A of the pixel electrode 7 is connected directly to the drain region 10 to make a contact. In this connection, however, the structure of FIG. 8 has the problem that any good contact is not possible owing to the reason set out below.
The semiconductor unit 2 is constituted of an amorphous silicon film or a polysilicon film, and the film is doped with ions to form n.sup.+ layers thereby forming the source region 9 and the drain region 10. These source and drain regions 9, 10, respectively, have a relatively great specific resistance of about 10.sup.-2 to 10.sup.-3 .OMEGA..times.cm. If the ITO pixel electrode 7 is formed directly on the regions 9, 10, there arises the problem that the electric resistance at the connections becomes great.
To avoid this, it is usual in prior art to diffuse a silicide of an element such as Cr, Ta, W or the like into the upper portions of the source and drain regions 9, 10 to form a thin silicide layer whose specific resistance is low (e.g. a specific resistance of about 10.sup.-4 .OMEGA..times.cm), ensuring the connections through the silicide layer. However, where the contact holes are formed in the insulating layer 3 for the formation of the connection terminal 7A, a problem is involved in that when over-etched, the silicide layers beneath the contact holes are etched and thus disappear. Thus, it becomes difficult to make good contacts ensuring low resistance connections. Moreover, Al is known as a material for interconnection which is low in specific resistance and which is unlikely to cause the delay of signals. Al is also known as an element which is difficult to make good contact with the ITO pixel electrode 7, thus presenting the problem that this material cannot be adopted in the structure shown in FIG. 8.